[英]Concurrent assignment to a non-net '_' is not permitted
I'm getting the error:我收到错误:
concurrent assignment to a non-net 'A' is not permitted
concurrent assignment to a non-net 'B' is not permitted
Static elaboration of top level Verilog design unit(s) in library work failed.
What am I doing wrong?我究竟做错了什么?
module ex1( input reg [1:0] a,
input reg [1:0]b,
output wire c,
);
assign c=(a>b)?(a=1'b1):(c=1'b0);
endmodule
module testbench(
);
reg[1:0]a=2'b11;
reg [1:0]b=2'b00;
wire c;
always#10
begin
a=a-2'b01;
b=b-2'b01;
end
initial
#150 $finish;
ex1 testbench2 (.a(a),
.b(b),.c(c));
endmodule
I get 3 syntax errors in your ex1
module.我在您的
ex1
模块中收到 3 个语法错误。
The trailing comma in a port list is illegal.端口列表中的尾随逗号是非法的。 Change:
改变:
output wire c,
to:至:
output wire c
It is illegal to assign a value to an input port inside a module.给模块内部的输入端口赋值是非法的。 This is illegal:
a=1'b1
.这是非法的:
a=1'b1
。 Assuming it was a typo to use a
there, and you really meant to type c
, you should change:假设在此处使用
a
是一个错字,并且您真的打算输入c
,您应该更改:
assign c=(a>b)?(a=1'b1):(c=1'b0);
to:至:
assign c = (a>b) ? 1'b1 : 1'b0;
You typically never want to make an assignment inside a conditional operator like your code does.您通常不想像您的代码那样在条件运算符中进行赋值。
One simulator also complains about declaring an input
port as a reg
type.一个模拟器还抱怨将
input
端口声明为reg
类型。 You should omit reg
for a
and b
.您应该为
a
和b
省略reg
。 Here is the recoded module:这是重新编码的模块:
module ex1 (
input [1:0] a,
input [1:0] b,
output wire c
);
assign c = (a>b) ? 1'b1 : 1'b0;
endmodule
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