[英]I'm trying to implement a convolution encoder. I have attached my code. I am a beginner in verilog and I don't think my testbench is working properly
`timescale 1 ns/1 ns
module VIT_ENC (Vx,Ux,tb_en,clock,reset);
`include "params_b213.v"
output [`n-1:0] Vx;
input [`k-1:0] Ux;
input tb_en;
input clock;
input reset;
reg [`m:0] encoder_reg;
always @(posedge clock or posedge reset)
begin
if(reset)
encoder_reg = 4'b0;
if (tb_en==1'b0)
encoder_reg = {Ux, encoder_reg[3:1]};
end
assign Vx[1] = encoder_reg[3]^encoder_reg[1]^encoder_reg[0];
assign Vx[0] = encoder_reg[3]^encoder_reg[2]^encoder_reg[1]^encoder_reg[0];
endmodule
The always block does not work for some reason.由于某种原因,always 块不起作用。 The encoder_reg is not getting any values.
encoder_reg 没有得到任何值。 How to assign values to a reg in an always block?
如何为始终块中的 reg 赋值? EDIT: I am adding the test bench code also here.
编辑:我也在此处添加测试台代码。 So we are giving some input to Ux, which has to get shifted and stored in encoder_reg.
所以我们向 Ux 提供了一些输入,这些输入必须被移位并存储在 encoder_reg 中。 Modulo 2 addition(XOR) is performed between the bits of encoder_reg and stored in the output.
在encoder_reg的位之间进行模2加法(XOR)并存储在output中。
`timescale 1 ns/1 ns
module tb_VIT_ENC();
`include "params_b213.v"
wire [`n-1:0] Vx;
reg [`k-1:0] Ux;
reg tb_en;
reg clock;
reg reset;
VIT_ENC
dut(.Vx(Vx),.Ux(Ux),.tb_en(tb_en),.clock(clock),.reset(reset));
initial
begin
Ux=1;tb_en=0;clock=1;reset=0;
#100;
Ux=0;tb_en=0;clock=1;reset=0;
#100;
Ux=1;tb_en=0;clock=1;reset=0;
#100;
Ux=0;tb_en=0;clock=1;reset=0;
end
endmodule
I can see that there is no clock signal generation in the test bench.我可以看到测试台中没有时钟信号生成。 Without a positive edge on the clock signal the registers are'nt going to work.
如果时钟信号没有上升沿,寄存器就不会工作。 You could use the following initial block in your test bench, instead of driving
clock = 1
every 100ns as written in your test bench.您可以在测试台中使用以下初始块,而不是在测试台中每 100ns 驱动
clock = 1
。
initial
begin
clock = 1'b1;
forever #5 clock = ~clock; //Clock Generator
end
The initial
block sets clock
to 1 initially. initial
块最初将clock
设置为 1。 The next line toggles the clock after 5ns and sets clock
to 0. The forever
keyword ensures the clock toggles every 5 time units forever till the end of the simulation, thus generating a square wave of period 10 time units.下一行在 5ns 后切换时钟并将
clock
设置为forever
关键字确保时钟永远每 5 个时间单位切换一次,直到模拟结束,从而生成周期为 10 个时间单位的方波。 (Given the timescale in your code 10 time units = 10 ns) (给定代码中的时间刻度 10 个时间单位 = 10 ns)
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