I have an 7 bit up/down counter written in Verilog code:
module updowncount_7bit (clock,reset,hold,up_down,q);
input clock,reset,hold,up_down;
output reg [6:0] q;
integer direction;
always @(posedge clock)
begin
if(up_down)
direction = 1;
else
direction = -1;
if (!reset)
q <= 0;
else if (!hold)
q <= q + direction;
end
endmodule
I have tried to write a test bench code but it's seem the output does not work and I don't know why ! Anyone can help !?
The Test-bench result :
In Model-sim:
In Quartus by Vector-waveform :
module counter_7bit_tb;
wire [6:0]f_tb;
reg clock_in_tb, reset_tb, hold_tb, up_down_tb;
updowncount_7bit dut(clock_in_tb, reset_tb,hold_tb, up_down_tb, f_tb);
initial begin
clock_in_tb = 0;reset_tb= 1; hold_tb = 0;up_down_tb=1;
#10;
forever begin
#10 clock_in_tb= ~clock_in_tb ;
end
end
endmodule
You don't seem to have applied reset
to your module from the testbench. Therefore q
will always be X
, which looks like what you're seeing.
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