简体繁体中英

how to write test bench for slave module in which it assign input values from master module?

原文 2016-04-21 15:27:14 7 1 verilog/ test-bench

I have written two Verilog modules so called master.v and slave.v in which master.v module provides output values and slave module is going to use these master's output values. Can you please advise me on how to write testbench for assigning Slave's input as master's output values?

1 answers

Take instance of Master.v and Slave.v in Testbench.v and connect respective wires(signals) and then drive necessary inputs like reset and clock to both master and slave instance if any. See below basic diagram.

How can i writing test bench for multiple module?

How to read input stimuli from file in a loop in systemverilog test bench?

How to write a test bench for ports of multidimentional arrays

How to I assign Don't Care values in truth table of test bench?

Verilog: How to assign the output of a module to a bus which have different width

How to save data using $fwrite() command from verilog test bench such that the values of the multiple outputs save in adjacent columns of a csv file?

How to assign an output of a module with variable?

How can I write an 8-bit array as input of a module in systemverilog

How to write to inout port and read from inout port of the same module?

How can I assign module arguments in Verilog?

暂无

The technical post webpages of this site follow the CC BY-SA 4.0 protocol. If you need to reprint, please indicate the site URL or the original address.Any question please contact:yoyou2525@163.com.

Related Question How can i writing test bench for multiple module? How to read input stimuli from file in a loop in systemverilog test bench? How to write a test bench for ports of multidimentional arrays How to I assign Don't Care values in truth table of test bench? Verilog: How to assign the output of a module to a bus which have different width How to save data using $fwrite() command from verilog test bench such that the values of the multiple outputs save in adjacent columns of a csv file? How to assign an output of a module with variable? How can I write an 8-bit array as input of a module in systemverilog How to write to inout port and read from inout port of the same module? How can I assign module arguments in Verilog?

Related Tags

how to write test bench for slave module in which it assign input values from master module?

Question

1 answers

solution1 0 2016-04-22 08:59:10

solution1
0 2016-04-22 08:59:10