While loop in test bench of and gate. getting no output

Question

I have written a simple test bench for and gate. My code and test bench was working fine. Now what I want to do is " I am trying to implement a while loop for my cases". I am not getting syntax error but not seeing any output. can any body tell my mistake?.

timescale 1ns / 100ps


int count=0;
module and_gate_test;

    // Inputs
    reg in1_t;
    reg in2_t;

    // Outputs
    wire out_t;

    // Instantiate the Unit Under Test (UUT)
    and_gate and_gate_1 (in1_t,in2_t,out_t);


    initial 
    begin
        // Initialize Inputs
        //case 0
        while(count==100){
        in1_t <= 0;
        in2_t <= 0;
        #1 $display ("out_t=%b",out_t);
                //case 1
        in1_t <= 1;
        in2_t <= 1;
        #1 $display ("out_t=%b",out_t);

        //case2
        in1_t <= 0;
        in2_t <= 1;
        #1 $display ("out_t=%b",out_t);

        //case3
        in1_t <= 1;
        in2_t <= 0;
        #1 $display ("out_t=%b",out_t);

       count++; }
        // Add stimulus here

    end

endmodule

Answer 1

hey i think you may want

 while( count <= 100) 

you were never getting into the while loop because you are starting at zero so

while(count==100)

never evaluates to true

Answer 2

the while loop you used will never be executed as count will never be equal to 100 as Alex Rellim said. It should be like

while(count<=100)

and also count++ will not work in verilog. Use

count = count + 1

instead of count++.

And also while loop should have begin and end instead of curly braces.

Answer 3

Couple of problems:

1. Curry brackets (ei { and } ) for the while-loop need to be replaced by begin and end respectively
   • The simulator has a bug if it is not generating a syntax error ans the current code doesn't follow Verilog or SystemVerilog allowed usage.
     
     
2. int count=0; needs to be inside the module
   • Note : int is SystemVerilog. Use integer if you want to strictly follow IEEE Std 1364. int is fine if you want to utilize IEEE Std 1800. int defaults as 32'd0 while integer defaults as 32'dX .
     
     
3. while(count==100) should be while(count<=100) or while(count<100)
   • if using == then the whole loop will be skipped since count is initialized as zero.
   • Alternative Solution for a loop: use for(integer count=0; count<100; count++) instead of while(count<100)

Answer 4

while(count == 100) ?!

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