Makefile for using make as gcc

Question

Is it possible to write universal Makefile which would get any target and act like a wrapper to gcc, but with parameters? For example, this means that

make 01.c

will have the same result as

g++ -o 01.out 01.c

Answer 1

make already has several "implicit rules" to do what you're trying.

For example, even with no makefile ,

make 01.o

Will run:

c++ -c -o 01.o 01.cpp

If it finds a file called 01.cpp in your current directory. You can set the CXXFLAGS environment variable if you want to pass more flags. If you're really set on using g++ rather than the system compiler, you can set CXX=g++ , too.

Answer 2

Yes - You using implicit rules.

Summat like (if memory serves me right)

.cpp.o:
    $(CCC) $(CFLAGS) $< -o $@

Maybe in the set of default implicit rules

Answer 3

You can use a wildcard - % .

However, the thing specified on the commandline is the target, not the source - what you want, not what you have.

It looks like what you want is approximately:

%.out: %.c
    g++ -o $@ $<

This means: to make (something).out, first make sure you have (something).c, then run g++ -o (something).out (something).c

$@ is always the target file, and $< is the first prerequisite.

You will need to run make 01.out , not make 01.c