Verilog Base 2 Clock Divider

Question

I am trying to take the 50 Mhz clock generated in lab7tb() and convert it to one with a period of 6 microseconds, or close to. When I run the waveform clockout is red and don't know why.

`timescale 1 ns/1 ns //time scale for the test bench


module p2divider(clockin, clockout); 
    input clockin; 
    output wire clockout; 

    parameter n = 9; 
    reg [n:0] count; 

    always@(posedge clockin) 
    begin 
        count <= count + 1; 
    end 

    assign clockout = count[n]; 
endmodule 


module lab7tb(); // the test bench module

    reg clock_sig;
    wire clock_out;



    // Instantiate the Unit Under Test (UUT)
    p2divider a (clock_sig, clock_out);


    integer i; 
    initial begin
        for(i=0; i<100; i=i+1)
        begin
            clock_sig <=1;
            #10;
            clock_sig <=0;
            #10;
        end
    end

endmodule

Answer 1

The register count needs to be reset at the beginning of sim.

When the module powers on, the value of count is unknown. If you keep adding 1 to an unknown value, it stays unknown forever.

You can use an initial statement to set count to 0 if this is targeted for an FPGA, or otherwise bring your reset signal into the block and set count to 0 when reset is asserted.