Treat signal as a clock in Verilog

Question

for example, here is the diagram from previous question in here which I want to ask.

If I treat an data like the diagram here, and write it into Verilog code What is the disadvantages here. thanks to answer.

Maybe there will be encounter some problems when we are synthesis or implementation in the tools that we use? but actually it's works okay here when I program the code above into my FPGA.

Answer 1

Short Answer
Unreliable Sporadic Behaviour!

Long Answer
FPGA & ASIC designs use what is sometimes called synchronous design methodology. The basic idea is that clock pins are always driven by a clock. This allows synthesis tools to perform an analysis called 'static timing' which gives a degree of confidence that the design will operate properly because the delays have all been analyzed to be within the designers constraints.

In the design shown, the delay on the Q output of the first stage will be a determining factor on the correct operation of the circuit. Designers want to reduce the dependence on delay reducing the concerns to those that can be performed by static timing analysis.

The style shown is used in older references (my college digital design textbook in the 90's had these) and is sometimes part of what is called a 'ripple counter'. This was a popular method of digital design prior to the prevalence of FPGA and ASIC. In those days digital circuits were done using discrete logic on a printed circuit board, and the design concerns were different.

Its a bit difficult to find information on this topic. This post discussis the same topic a bit but does not go deep on the main point.
https://electronics.stackexchange.com/questions/115967/what-is-a-ripple-clock
One reason that its difficult to find information is that the term 'asynchronous design' has different meanings, and the more ubiquitous meaning pertains to the design of digital circuits where feedback around combinational logic is used. The logic settles or 'latches' into a stable state. This is different than the discussion whose main idea is 'always drive clock pins with a clock'

Another bad practice that was part of asynchronous design was to use the asynchronous reset pin of a flip-flop as control logic. In synchronous design the asynchronous reset pin is often not used, and when it is used, its asserted asynchronously, de-asserted synchronously and used mostly for global power on resets. This is a reply to a similar issue discussed on the Xilinx question & answer forum. https://support.xilinx.com/s/question/0D52E0000757EsGSAU/that-dangerous-asynchronous-reset?language=en_US
The author (Xilinx engineer Ken Chapman) used the phrase 'Unreliable Sporadic Behavior' in the answer.

Another (good) synchronous design practice is to use very low skew clock resources to distribute the clock, so that the clock effectively is changing at the same time everywhere in the physical part.

Use synchronous design techniques & static timing as part of verification and to save debug effort for more important issues.

The term 'synchronous design' has kind of been forgotten since the 90's and is not widely used, its just the way designs are done. Google searching 'static timing' would be helpful to understand these concepts. A complete answer to 'what is static timing analysis' is beyond the scope of this question.

Do the following as a basis for synchronous design:

• Drive clock pins with a clock
• Use a clock buffer or clock tree to distribute the clock
• Have a corresponding reset for each clock
• Don't use asynchronous reset pins as control
• Learn how to cross clock domains
• Specify a timing constraint for each clock
• Perform static timing analysis, understand the results