Sytem Verilog Testbench: Apply initial time offset to clock signal

Question

If my clock signal toggles every 40ns but I want it to start toggling only after a specific delay, let's say 15ns, how can I do so using verilog testbench?

Answer 1

initial begin
    clock = 0;
    #15ns;
    forever #40ns clock = ~clock;
end