Verilog testbench - use task to drive a signal from an included file?

Question

I'm simulating a design that uses an FPGA and CPU. The CPU communicates with the FPGA via SPI, and the FPGA controls some outputs based on the communicated data.

I've got the simulation up and running and my simulated CPU testbench can read and write to FPGA registers via SPI. Now I want to refactor my code to make it a bit cleaner.

I've got several tasks that send data via SPI in my top level testbench, called tb_system_interface.v , which contains the tb_system_interface module that is instantiated by the testbench. The lowest level task is called spi_send_byte which sends data out the MOSI line, receives it on the MISO line and drives SCLK. Other higher level tasks read and write registers on the FPGA that control the outputs (eg set PWM value, set output value, etc)

I tried to refactor the SPI transaction to a new file, called tb_sim_spi_tasks.v . The I include this file in the tb_system.v file. Of course, now my spi_send_byte task doesn't work, because it is no longer inside the module that has the SPI signals in it.

Is there a way to do what I'm trying to do? Would it be possible to spread the module definition across multiple files? Or some sort of global variable that the task can set that would be output by my testbench?

Answer 1

I found out how to do this, I was including the file from the wrong location. Instead of all the includes at the top, the include needed to be inside the module. The following was the original code:

`timescale 1ns/100ps
`include "ch_defines.v"
`include "tb_sim_spi_tasks.v"

module tb_system_interface(
    output reg SYSTEM_EXTERNAL_RESET_N, 
    output reg SYSTEM_CLOCK, 

    output reg system_sclk, 
    output reg system_mosi,
    output reg system_cs_n,
    input wire system_miso,


    input wire sys_ok // Flag that CCC is locked

);
parameter SYSCLK_PERIOD = 10; // 10ns period = 100MHz.  

And this is the fix:

`timescale 1ns/100ps
`include "ch_defines.v"

module tb_system_interface(
    output reg SYSTEM_EXTERNAL_RESET_N, 
    output reg SYSTEM_CLOCK, 

    output reg system_sclk, 
    output reg system_mosi,
    output reg system_cs_n,
    input wire system_miso,


    input wire sys_ok // Flag that CCC is locked

);

`include "tb_sim_spi_tasks.v"

parameter SYSCLK_PERIOD = 10; // 10ns period = 100MHz.