my input in systemverilog is in bits; but I need it to be in uint8_t. is API or library can do it? FYI, Im trying to verify verilog results with .C us ...
my input in systemverilog is in bits; but I need it to be in uint8_t. is API or library can do it? FYI, Im trying to verify verilog results with .C us ...
I need to generate around 10,000 connectivity assertions to check that values driven at DUT interface at the beginning of simulation has reached (and ...
I have a very complicated packed struct, C, with nested packed structs, A and B, in SystemVerilog: I need to send this struct via a DPI-C call and ...
I wonder if the modules have any visibility into the hierarchy of the ports? Can the port hierarchy be printed out? For a minimum working example, as ...
While using DPI in SystemVerilog I faced an issue to redirect stdout of C side into stdout of SystemVerilog to get all log writes in one place (In my ...
I would like my array of data from SystemVerilog have the entire copy of data from the array on the C/C++ side: C/C++ code: SV code: My issue i ...
Would it be possible to export to C a task defined inside a SystemVerilog class as the following? ...
Instantiate the following module connecting ports by name. The output of the module should be connected to wire S, port B should connect to wire T, an ...
ModelSim User's manual (v10.1c), in page 660, talks about the default autocompile flow (using vlog) and external compilation flow to get the the DPI-C ...
I am writing a DPI checker(.cpp file), In this, Checker reads the 128-bit value on every line and I want to mask it with a 128-bit mask and compare it ...
How do I detect the timescale precision used in a simulation from the source code ?. Consider I have a configuration parameter(cfg_delay_i) of some de ...
I want to use a dynamic array inside a struct which i pass onto C using DPI. How do i implement it on C-side. I tried using svOpenArrayHandle inside ...
What is the equivalent syntax or implementation for System verilog‘s $value$plusargs option in Specman E ? I am working in converting a source code ...
What is the equivalent syntax in Specman E for $readmemh(file,array) and similar system tasks and functions in System verilog? I am working in conver ...
Is there any way I can connect an apb master vip to internal module inside dut which have apb signals in it . I want to program some registers in this ...
I try to import some C-function that generates an array in SystemVerilog. Here is code: #include "svdpi.h" #include <stdlib.h> #include <std ...
In systemverilog sv_define.vh In C c_define.h Since syntax for "define" is different between systemverilog and C. If I want to config ENABLE, I ...
I am trying to run a UVM simulation and I use a C code for predicting the output but I get the warning mentioned above when running the simulation. Wi ...
I am trying to verify a sMEM design using assertions in systemVerilog however I got a problem I did not Know How to solve it : I am supposed to verify ...
I have a fork-join_none block in forever loop in SV which has two threads. One thread is a call to a task in SV itself. The other thread is a call to ...