Get port name in SystemVerilog

Question

I wonder if the modules have any visibility into the hierarchy of the ports? Can the port hierarchy be printed out?

For a minimum working example, assume I have this:

module top ();
  
  logic my_sig;

  child ichild (.sig(my_sig));

endmodule : top


module child (input logic sig);
  
  initial $display(/* SystemVerilog-Fu here */)

endmodule : child

I expect the $display to print top.my_sig -- or something that conveys my_sig name instead of just reading out the value. I looked into the DPI guide as well, but it doesn't seem to have any such facility.

Thanks in advance!

Answer 1

The DPI is for behavioral modeling interoperability between SystemVerilog and C. The VPI gives you the introspection you are looking for in from C. Also, many tools have a command line interface ( find signals -ports in Modelsim/Questa without having to learn a complicated C API.

Explaining how to do this is too deep a discussion for SO . I suggest you read my DVCon 2016 paper on SystemVerilog introspection with examples here .