Verilog clock generator error?

Question

I write simple code using ISE 14.7 to generate clock signal, but the output in iSim is always 1, until I change = with <= then the clock works, could you tell me why?

module nonblocking( clk );
 output reg clk;

 initial 
   #10 clk =0;

 always @ (clk)
#10 clk = ~ clk; // change to <= to work

endmodule

Answer 1

This code honestly doesn't make any sense.

Your current code states that based on clk , the value of clk should be ~clk . When you use <= you are at least specifying a nonblocking assignment, which makes slightly more sense, but still doesn't.

If you want a clock generator for simulation, use the following within an initial block (giving a 10ns period):

forever begin
    #5 clk <= ~clk;
end

If you want a clock generator for FPGA synthesis, either connect a physical oscillator to your device's clock input pin, or use a built-in oscillator (if available on your device). You can always use a DCM/PLL/CMT/MMCM/whatever your FPGA calls it to adjust the clock frequency.