Verilog Clock Pulse

Question

I have 2 clocks, fast clock and slow clock. I am trying to make a clock pulse trigger by the rising edge of the slow clock, with duration of 1 fast clock cycle. I have managed to create similar as shown, but this is using an arbitrary counter, and I need to guarantee it will happen on the rising edge of the slow clock. Ideas appreciated.

module clock_check;
  
  reg clk18M = 1'b0;
  
  always #1 clk18M <= ~clk18M;
  
  wire clk6M;
  wire clk_puls;


  
  reg [4:0] clk18div = 5'b00000;
  always @( posedge clk18M ) clk18div <= clk18div+5'd1;

  assign clk6M  = clk18div[4];
  assign clk_puls  = clk18div[4:0]==5'b10000;
  
  initial
  begin
    #200;
    $finish();
  end
    
  initial 
  begin 
    $dumpfile("dump.vcd");
    $dumpvars(0);
  end
  
endmodule 

Answer 1

I think this will do what you need. It has two outputs, choose which one is best suited for your need. Output LED1 is optimised to keep the latency and jitter of the rising edge as low as possible.
The other output sacrifices latency and jitter for keeping the pulse width constant. I don't think there is a way that can guarantee both low latency and constant pulse width.

This of course is assuming your two clock signals are not synchronised. If they are then that problem goes away.

It will cope with variations in frequency of the clocks as there is nothing like the arbitrary counter you wanted to get rid of.

With some small modifications you can change the pulse with between being equal to the period of the fast clock or half of it.

The PLL in the code is just a stand in for the clock signals you have, which I'm assuming are some external signal.

Here I deliberately made the two clocks not be exact multiples so I would have a different delay between the rising edges on each cycle to set a worst case scenario.

For that reason I set the two clocks at 25MHz and 2.4MHz respectively. The 400MHz clock is just for the SignalTap analyzer, to give it a much higher sampling rate than the signals it is recording.

module Cyclone5FirstTest
(
    input   clk50MHz,
    output  LED1,
    output  LED2,
    output  fClock,
    output  sClock,
    output  refClock    
);

    reg prevState1;
    reg prevState2;
    reg pulseOut;
    wire fastClock;
    wire slowClock;
    
    assign fClock = fastClock;
    assign sClock = slowClock;
    assign LED1 = ( sClock==1 && prevState1==0 );
    assign LED2 = ( prevState1==1 && prevState2==0);
        
    PLL_1 PLL_1
    (
        .refclk         (clk50MHz),
        .outclk_0   (fastClock),        // 25MHz
        .outclk_1   (slowClock),        // 2.4MHz
        .outclk_2   (refClock)          // 400 MHz - clock for logic analyzer
    );
    
    always @(posedge fastClock)
    begin
        if ( slowClock & !prevState2 ) pulseOut <= 1;
        else    pulseOut <= 0;
        prevState1 <= slowClock;
        prevState2 <= prevState1;
    end

endmodule

SignalTap trace