I am working on a piece of code in which I need to generate output as per the condition-
1. if input is X/Z output should be X. 2. if input is 0 output should be 0 with a delay of 0.75us. 3. if input is 1 output should be 5 high going pulses of 1.5us with 50% duty cycle with a delay of 0.75us.
I am confused How to write it in verilog?
You can use SystemVerilog's fork/join_none
for this
logic in, out;
always begin
fork
case (in)
0: out <= #0.75us 0;
1: repeat (5) begin
#0.75us out <= 1;
#0.75us out <= 0;
end
default: out <= 'x;
endcase
join_none;
@in
disable fork; // kill repeat loop if still active
end
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