Writing data on Negative edge clock, without using negedge clock [verilog]

Question

I want to use the posedge clock only, but i want to write data on the negative edge of the clock. The next image is more explanatory of the problem spi Interface

In the spi slave, mode 3 the data is sampled in negative edge clock, but how can i implement it in verilog using only posedge clock?

Answer 1

The only thing that comes in my mind is to implement a clock negator in the top module. Then the actual negedge of the clock will be the posedge of the module. In the top module you should implement a mux for choosing which edge will come as input, depending on the mode.

Ie

case(mode) Mode_1: begin assign clk2=clk; end Mode_3: begin assign clk2 =~clk; end endcase