What is the merit to using the negedge clock in verilog?

Question

Now I'm trying to understand the merit what we using the negedge clock in verilog. I came across as the below verilog code in the google.

module negedgecapture
   ( 
    input              clk,
    input              rst_n,
    input              din,
    output wire        dout
    );

   reg           neg_dout    ;
   assign dout = neg_dout;

   always @(negedge clk or negedge rst_n)
     if (~rst_n) neg_dout <= 0;
     else neg_dout <= din;

endmodule 

and in case, as I know, the setup time is at least required time the data to become stable before the clock edge. and hold time is at least required time the data to become stable after the clock edge.

But I don't know what benefits are in there? why we use those kinds of Technic?

Answer 1

If you are writing on a posedge, reading would be useful on a negedge. That would save one full clock cycle on a read operation.

Negedge clock operation is also used in testbenches, to avoid race condition between DUT and Testbench, since both are driven at different clock edges.

Answer 2

There is no particular advantage to using the falling edge of a clock as opposed to the rising edge to clock a register. In fact, most designs I've worked on using a rising edge for everything. There are a few cases where I've seen the negative edge used though:

1. When working with an external interface that uses a negative for some reason. I seem to recall that a long time ago ie in the days of bipolar TTL logic, the I/O drivers may be asymmetric with regards to rise and fall time, with the fall time being faster. In some cases, this behaviour got grandfathered into the interface design.
2. On some older ASIC designs, designers would switch from one clock edge to the other when moving between blocks to avoid clock skew issues. However, since then, layout tools have got better at using managing clock skew, so this process is no longer used.
3. On DDR (double data rate) interfaces, data changes on both the positive and negative clock edges. You'll see this in LVDS based I/O and DDR memory interfaces.