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Verilog, handshakes and clock rates

原文 2013-11-21 07:51:23 1 1 verilog

OK, I'm new to this.

Just wondering, when designing modules, do I have to do handshakes between modules?

Or can I just assume that combinational logic in an 'always' block will always finish before the next clock - that the compiler (or what have you) will select a suitable clock rate.

1 answers

When designing a hardware based system you usually define you clock frequency, for certain platforms it may be predefined 50MHz, 100MHz etc.

In RTL or behavioural simulations the combinatorial logic will have no time delay through it. When synthesising the RTL in to gates, you apply constraints, eg clock frequency. To be timing safe the synthesis tool must create combinatorial logic with a lower propagation delay than your clock period.

If you are not timing clean, then this constraint is broken and you have to slow your clock down giving you more time or break up the logic by inserting flip-flops.

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Verilog, handshakes and clock rates

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solution1 1 ACCPTED 2013-11-21 08:58:23

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1 ACCPTED 2013-11-21 08:58:23