I have a Makefile that compiles the source to object files, and it works:
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp
g++ $(FLAGS) $(INCLUDES) -c -o $@ $<
but it includes all the files from my src directory. Say I have some file (eg "x.cpp") that I don't want as a part of my compilation. I'd like to manually specify only some files to compile into objects. For example,
SRC = src/one.cpp src/two.cpp
OBJ = obj/one.o obj/two.o
$(OBJ_DIR)/%.o: $(SRC)
g++ $(FLAGS) $(INCLUDES) -c -o $@ $<
I'd get one.o, two.o, but NOT xo Is this possible somehow?
Define a list of modules, construct the list of objects you actually want:
MODULES = one two
OBJECTS = $(addprefix ${OBJ_DIR}/, $(addsuffix .o, ${MODULES}))
all : ${OBJECTS}
Restrict the rule to those in the list:
${OBJECTS}: $(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp
g++ $(FLAGS) $(INCLUDES) -c -o $@ $<
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