Rocket core implements the RV64G version of RISCV?

Question

I wanted to know , which version of the riscv ISA is the released rocket core capable of implementing.

Since it supports Double precision floating point , am i safe to assume that it is the RV64G version .

Answer 1

Yes, the Rocket core implements RV64G.*

If you'd like to manually verify this yourself, you can check the ctrl code 's decode tables.

However, you can turn off the FPU in the parameter settings of the rocket-chip generator, by setting case BuildFPU =>... to None (or by invoking the SmallConfig when building Rocket from the command line).

Fun fact, in inspecting the decode tables, you can also see additional custom extension instructions used to implement the "RoCC" interface, which communicates with any attached accelerator/co-processor cores ("ROcket Coprocessor Coordination"). By default they are off, as buildROCC is set to None .

*Edit: As you point out, Rocket (currently) eschews implementing the fdiv and fsqrt instructions. These will trap and will be executed in software (assuming you are running Rocket on top of a kernel that implements these instructions). In fact, the current riscv-gcc port will not emit these instructions by default, but will instead emit soft-float versions on fdiv and fsqrt.

References

• ctrl code
• parameter/configuration file
• core code
• chip code