Using foreach loop in makefile with tcsh shell

Question

I'm trying to run:

SHELL   =/usr/bin/tcsh
foo: 
    @foreach i ( "a" "b" "c")\
    echo $$i\
    end

But I get this error

i: Undefined variable.
make: *** [foo] Error 1

I found this question and answer , but looks like it uses bash, not tcsh.

Answer 1

The short answer is, you should not ever use tcsh , at least not for makefiles. My personal opinion is that it's high time csh and all derivatives were relegated to the dustbin of history, for all purposes. But they definitely are not usable in makefiles.

From that link, note for example: You can't combine multiline constructs in a csh using semicolons.

In addition to the problems they have with single-line scripts, they won't work with make's parallel jobserver support because they do nasty things with file descriptors.

Answer 2

SHELL = /usr/bin/tcsh
# but we can't use its loop constructs as they're multi-line

foo: 
    @sh -c 'for i in a b c; do echo $$i; done'