Verilog module output reg driving output reg?

Question

So I'm trying to instantiate a module within a module. The root module has output ports that drive the output pins and I want the inner module to drive those ports directly but I can't get it work anyway round.

/*
A root module for the 005_135-scanner_mainboard_revA_sch-pcb. Can be used as a test bench for testing peripheral devices but has been designed to be the master root module for the final code.
All IO is included and reset pins on peripheral devices driven active reset with data lines driven to an appropriate value (located in the ‘initial block’).
George Waller. 09/08/15.
*/

module root_module( ft_reset, ft_usb_prsnt, ft_bus_pwrsav, ft_bus_oe,             ft_bus_clkout, ft_bus_siwu, ft_bus_wr, ft_bus_rd, ft_bus_rxf, ft_bus_txe, ft_bus_d,
                        mtr_fault, mtr_config, mtr_m1, mtr_m0, mtr_rst, mtr_out_en, mtr_step, mtr_dir,
                        ccd_driver_oe, ccd_p1, ccd_p2, ccd_cp, ccd_rs, ccd_sh,
                        dac1_sdin, dac1_sclk, dac1_sync, dac2_sdin, dac2_sclk, dac2_sync,
                        adc_pwrdn, adc_encode, adc_d,
                        fpga_reset,
                        clk,
                        gpio,
                        led_ctrl,
                        leds);

//Input declarations
input wire          ft_usb_prsnt, ft_bus_clkout, ft_bus_rxf, ft_bus_txe,
                        mtr_fault, 
                        fpga_reset,
                        clk;

input wire [7:0]    adc_d;

//Output declarations
output reg          ft_reset, ft_bus_pwrsav, ft_bus_oe, ft_bus_siwu, ft_bus_wr, ft_bus_rd,
                        mtr_config, mtr_m1, mtr_m0, mtr_rst, mtr_out_en, mtr_step, mtr_dir,
                        ccd_driver_oe, ccd_p1, ccd_p2, ccd_cp, ccd_rs, ccd_sh,
                        adc_pwrdn, adc_encode,
                        led_ctrl;

output reg          dac1_sdin, dac1_sclk, dac1_sync, dac2_sdin, dac2_sclk, dac2_sync;

output reg [7:0]    leds;

//Input output declarations.
inout reg  [7:0]    ft_bus_d;

inout reg [16:0]    gpio;

//Variables go here     

integer count, count1, state, pixel_n, line_n, t_int;   
integer data[8];

reg en;

//Initial values on start up.
initial
begin
    //IO initial setup values.
    ft_reset = 1; ft_bus_pwrsav = 1; ft_bus_oe = 1; ft_bus_siwu = 0; ft_bus_wr = 1; ft_bus_rd = 1;  //NEED TO APPLY REAL VAULES!!!
    mtr_config = 1; mtr_m1 = 1; mtr_m0 = 1; mtr_rst = 1; mtr_out_en = 1; mtr_step = 0; mtr_dir = 0;
    ccd_driver_oe = 1; ccd_p1 = 0; ccd_p2 = 0; ccd_cp = 0; ccd_rs = 0; ccd_sh = 0;
    dac1_sdin = 0; dac1_sclk = 0; dac1_sync = 0; dac2_sdin = 0; dac2_sclk = 0; dac2_sync = 0;
    adc_pwrdn = 0; adc_encode = 0;
    led_ctrl = 0;
    leds = 0;
    gpio = 0;
    ft_bus_d = 0;

    //Variables setup values.   
    count = 0;
    count1 = 0;
    state = 0;
    pixel_n = 0;
    line_n = 0;
    t_int = 10000;  //t_int = integration time. integration time (seconds) =                  t_int * 10x10^-9. 
end //End initial

//Some other code goes here.
always @(posedge ft_bus_clkout)
begin
    if(count == 50000000)
        begin
            en <= 1;
            count = 0;
        end
        else
        begin
            en <= 0;
            count = count + 1;
    end 
end //End always

AD5601_module AD5601(.en(en), .clk(clk), .data(127),.sdout(dac1_sdin),
.sclk(dac1_sclk), .sync(dac1_sync));    

endmodule   //End module. 

And the inner module:

module AD5601_module(en, clk, data, sdout, sclk, sync);

        input wire          clk;
        input wire          en;
        input wire [7:0]    data;

        output reg          sdout, sclk, sync;

        integer sclk_count;
        integer data_state;
        integer delay_counter;
        integer pd[2];

        initial
        begin
            sclk_count = 0;
            data_state = 99;
            delay_counter = 0;
            pd[0] = 0;
            pd[1] = 0;

            sdout = 0;
            sclk = 0;
            sync = 1;
        end

        always @ (posedge en)
        begin
            if(data_state == 99)data_state <= 0;
        end


        always @ (posedge clk)
        begin
            if(sclk_count == 49)
            begin
                sclk_count = 0;
                sclk = ~sclk;
            end
            else sclk_count = sclk_count + 1;

        end

        always @ (posedge sclk)
        begin
            case(data_state)
                0:  begin
                    sync = 0;
                    sdout <= pd[1];
                    data_state <= 1;
                end

                1:  begin
                    sdout <= pd[0];
                    data_state <= 2;
                end             

                2:  begin
                    sdout <= data[7];
                    data_state <= 3;
                end             

                3:  begin
                    sdout <= data[6];
                    data_state <= 4;
                end             

                4:  begin
                    sdout <= data[5];
                    data_state <= 5;
                end             

                5:  begin
                    sdout <= data[4];
                    data_state <= 6;
                end             

                6:  begin
                    sdout <= data[3];
                    data_state <= 7;
                end             

                7:  begin
                    sdout <= data[2];
                    data_state <= 8;
                end             
                8:  begin
                    sdout <= data[1];
                    data_state <= 9;
                end             

                10:begin
                    sdout <= 0;
                    if(delay_counter == 6)                          
                    begin
                        data_state <= 99;
                        delay_counter <= 0;
                        sync = 1;
                    end
                    else delay_counter = delay_counter + 1;
                end             
            endcase
        end
endmodule

So with the code as is I get the error

'output or inout port should be connected to a structural net expression'

.

If I change the outputs in the root module or the inner module to wire I get the error 'the expression on the left hand side should be of a variable type'.

So at this point I have no idea how you nest outputs! Some help would be appreciated!

Thanks

Answer 1

inout ports should be a net type ( wire or tri ) and not a reg . A reg does not have conflict resolution (when there are two or more active driver). An inout should not be assigned in a procedural block (eg always -block, initial -block). It should be a simple assign statement as below. The designer must ensure there is only on active driver on the IO at any point.

assign io_port_name = driver_enable ? io_out_value : 'bz; // io_out_value should be a flop

An output should only be declared an output reg if it is assigned in a procedural block (eg always -block, initial -block) within the current module. All other outputs should be output or output wire (these identifiers are synonymous; the former is implicit while the latter is explicit). An should only be assigned within one always . FPGAs allow initial blocks, ASIC/IC does not.

If SystemVerilog is enabled, replace output reg with output logic . logic can be used for flops and single directional nets. logic is not recommended for inout ; logic like reg does not have conflict resolution.

The arrays integer data[8]; and integer pd[2]; are SystemVerilog syntax and not compatible with Verilog. Either enable SystemVerilog or change to integer data[0:7]; and integer pd[0:1];
SystemVerilog can be enabled per file by changing the file extension from .v to .sv ; recommended. Simulators/synthesizers typically have a switch to force all Verilog to be treated as SystemVerilog; not recommended, refer to the simulator/synthesizer manual if desired to go this route.