VHDL process assignment does not work

Question

I do have following VHDL code snipped:

signal state_last_pushbutton                    : std_logic;    

process (clk_clk)
begin
    if rising_edge(clk_clk) then
        userleds_external_connection_export(0) <= '0';
    else
        userleds_external_connection_export(0) <= '1';
    end if;

    state_last_pushbutton <= pushbuttons_external_connection_export(0); 

end process;

Question:

Why the signal state_last_pushbutton never gets the value of pushbuttons_external_connection_export(0) ? In the simulation its value remains always 'U'.

Thanks

Answer 1

It seems like you are trying to write a clocked process, in which case you should probably write something like this:

signal state_last_pushbutton : std_logic;    

process (clk_clk)
begin
    if rising_edge(clk_clk) then
      state_last_pushbutton <= pushbuttons_external_connection_export(0); 
    end if;
end process;

This will update state_last_pushbutton to the value stored in the register or signal pushbuttons_external_connection_export(0) on each rising edge of the clock.

Have you checked that pushbuttons_external_connection_export(0) is actually set to some known value, and that your clock is running properly?