How to pass a constant array as a module parameter?
I want to build a shift register width different shift widths. The possible shift widths should be definable via a module parameter. I tried something like the following, but this not working.
module ShiftReg
#(
SHIFT_WIDTH = '{1, 2, 4, 8},
WIDTH = $clog2($size(SHIFT_WIDTH))
)
(
...
input logic [WIDTH-1:0] shift_rate_i,
...
);
...
endmodule
This results in following error message:
** Error: shift_reg.sv(3): Illegal concatenation of an unsized constant.
Is such a generic construction of a shift register with different widths possible in SystemVerilog?
Not every simulator supports arrayed parameters. For those that do, the array needs to be defined with an array identifier (ex: []
, [SIZE]
) and a bit width for the entries; int SHIFT_WIDTH [] = '{1, 2, 4, 8}
should work.
I tried different combinations on EDAplaygroud . Queued arrays ( [$]
) was not accepted by any simulator. VCS supported []
arrayed parameters, but it does not accept it with $size()
or .size()
in a parameter definition. A fixed array size does work on VCS and Riviera-PRO. Declaring the size is an extra step, but it works.
module ShiftReg
#(
SIZE = 4,
int SHIFT_WIDTH [SIZE] = '{1, 2, 4, 8},
WIDTH = $clog2(SIZE)
//WIDTH = $clog2($size(SHIFT_WIDTH)) // <-- this also works if SHIFT_WIDTH is a fixed size
)
(
...
input logic [WIDTH-1:0] shift_rate_i,
...
);
...
endmodule
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