Verilog promote one-bit wire to 64-bit bus

Question

I have a 64-bit bus, and I would like to & every bit of the bus with a one-bit wire. What's the best way to do this? I would like to do something like below, but it doesn't seem to work as expected.

logic [63:0] bus, other_bus;
logic signal;
...
bus = other_bus & signal;

Answer 1

Replicate signal 64 times. Refer to the IEEE Std 1800-2012, section 11.4.12.1 "Replication operator":

bus = other_bus & {64{signal}};

Answer 2

you can also try this :- for (i=0,i<=63;i++) begin:ANDLoop bus[i] = other_bus[i] & signal; end:ANDLoop for (i=0,i<=63;i++) begin:ANDLoop bus[i] = other_bus[i] & signal; end:ANDLoop