Adding delay to clock for razor flip flop

Question

i am doing a project in vedic

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multiplier wherein i have to use razor flip flop where i have a main clock to one flip flop and another delayed clock to another flip flop and compare .can anybody say how to give to delay to clock # is not working.delay must meet setup time of both flip flops

Answer 1

In the Razor proposal, a Razor flip-flop consists of a pair of a normal edge-triggered flip-flop, and a "shadow latch" triggered by a delayed version of the clock. You can implement this by using a PLL to shift the clock by a known phase shift (assuming the clock's frequency is within the range of the PLL's VCO, this is straightforward). The shadow latch may be a level sensitive latch as is available on some FPGA hardware, or you may use a particularly late edge trigger and sacrifice some of the benefits of the Razor design in order to work with your available storage/register resources.