简体繁体中英

Unexplained Red X's (collisions?) with Dual-Port BRAM in Xilinx ISim

原文 2016-03-27 07:09:09 6 2 vhdl/ xilinx/ modelsim

I've read up on this quite a bit and I can't figure out why I would have Red X's (Collisions?) with a simple Dual-Port BRAM IP core.

I think there are only a few scenarios that can cause this:

Multiple sources: I checked and I don't have multiple sources diving current_row_data_out. I only read from it.

Simultaneous Read + WRite to the same address: Nope. As you can see in the image, read_addr and write_addr are always different.

What else can it be?

2 answers

The issues was caused by one or two writes of uninitialized data all the way in the beginning of the simulation. It created a chain-reaction that didn't show up until later because the values read in the beginning were coincidentally correct.

I don't know if this is helpful, but in case someone made the same stupid mistake as me, I'll put my case here.

I accidentally initialized the wire of dout to be 0, which doesn't give me an compilation error but when the output lines are not 0s, it will give me X.

Creating large dual-port RAM in VHDL

Simulating VHDL Modelsim Dual-port RAM with 2 Clocks

Xilinx / ISim seem claims value to be X but it has been declared

Increasing the speed of Xilinx ISim simulation

FPGA BRAM Stack Implementation Xilinx 7-Series

Xilinx Floating Point Core - Erroneous 'X' values?

Generating Single Port ROM on Spartan 6 using Xilinx ISE Design Suite

VHDL Dual Port RAM unexpected latches generated

BRAM_INIT in VHDL

combine ports to bram interface

暂无

The technical post webpages of this site follow the CC BY-SA 4.0 protocol. If you need to reprint, please indicate the site URL or the original address.Any question please contact:yoyou2525@163.com.

Related Question Creating large dual-port RAM in VHDL Simulating VHDL Modelsim Dual-port RAM with 2 Clocks Xilinx / ISim seem claims value to be X but it has been declared Increasing the speed of Xilinx ISim simulation FPGA BRAM Stack Implementation Xilinx 7-Series Xilinx Floating Point Core - Erroneous 'X' values? Generating Single Port ROM on Spartan 6 using Xilinx ISE Design Suite VHDL Dual Port RAM unexpected latches generated BRAM_INIT in VHDL combine ports to bram interface

Related Tags

Unexplained Red X's (collisions?) with Dual-Port BRAM in Xilinx ISim

Question

2 answers

solution1
0 ACCPTED 2016-03-28 22:51:34

solution2
0 2019-03-21 21:27:53

Unexplained Red X's (collisions?) with Dual-Port BRAM in Xilinx ISim

Question

2 answers

solution1 0 ACCPTED 2016-03-28 22:51:34

solution2 0 2019-03-21 21:27:53

solution1
0 ACCPTED 2016-03-28 22:51:34

solution2
0 2019-03-21 21:27:53