Looking for a good point to start customizing the Chisel source for rocketchip generator

Question

I've installed the riscv toolchain, and generated the verilog source with the default configs using the rocketchip generator source in the master branch at https://github.com/ucb-bar/rocket-chip .

I'm looking to understand the chisel source so I can try out modifications on the Chisel source, and I'm not sure how I should get started with this. For example, in the src/main/scala/TestConfigs.scala file - line 87 has the following code-

    class WithPrefetches extends Config(
      (pname, site, here) => pname match {
        case "COMPARATOR_PREFETCHES" => true
        case _ => throw new CDEMatchError
      })

I'm curious about why COMPARATOR_PREFETCHES is allowed as a case, and I'm trying to figure out what is "allowed" and where I can see these "definitions".

A push in the right direction is appreciated.

Answer 1

The place to start is src/main/scala/Configs.scala (TestConfigs.scala is used for generating test structures, not the actual processor). There are many examples present of how to generate various flavors of Rocket. As a concrete example, let's say you wanted to modify the default core to remove the FPU and increase the DCache associativity. You could write:

class MyBetterCore extends Config (
    topDefinitions = { (pname,site,here) => pname match {
      case UseFPU => false
      case _ => throw new CDEMatchError
    }},
  knobValues = {
    case "L1D_WAYS" => 8
    case _ => throw new CDEMatchError
  }
)

class MyBetterConfig extends Config(new MyBetterCore ++ new BaseConfig)

Then you could build and simulate this core by setting the CONFIG command-line variable:

make CONFIG=MyBetterConfig

All of the parameters that are safe to modify out of the box are located in Configs.scala .