error in verilog code of object on left side should be assigned a variable

Question

I have been trying to make an asynchronous fifo in verilog but I'm facing a problem of object "empty" and "full" on left side of assignment should have variable data type.

Top module:

module async_fifo (reset, wclock, rclock, datain, dataout, e, f);
input [15:0] datain;
output reg [15:0] dataout;
//reg [15:0] mem1, mem2, mem3, mem4, mem5, mem6, mem7, mem8;
reg [15:0] mem [7:0];
input reset, rclock, wclock;
/*reg [0:2] wptr, rptr;
initial wptr = 3'b000;
initial rptr = 3'b000;*/
integer wflag = 0, rflag = 0;
wire empty , full;
input e,f;
reg [0:2] wptr = 3'b000, rptr = 3'b000;

counter c(wclock, rclock, empty, full);
e = empty;
f = full;

always@(posedge wclock)
    begin
        if(f == 1'b0)
        begin
            e = 1'b0;
            if (wptr < 3'b111)
                begin
                    mem[wptr] = datain;
                    wptr = wptr + 3'b001;
                end

            else if(wptr == 3'b111 && wflag == 0)
                wflag = 1;

            else if (wflag == 1)
                begin
                    wptr = 3'b000;
                    wflag = 0;
                end 
        end
    end

always@(posedge rclock)
    begin
        if(e == 1'b0)
        begin
            f = 1'b0;
            if (rptr < 3'b111)
                begin
                    dataout = mem[rptr];
                    rptr = rptr + 3'b001;
                end

            else if(rptr == 3'b111 && rflag == 0)
                rflag = 1;

            else if (rflag == 1)
                begin
                    rptr = 3'b000;
                    rflag = 0;
                end 
        end
    end
endmodule   

Counter module:

module counter(w_clock, r_clock, empty, full);
input w_clock, r_clock;
output reg empty = 0, full = 0;
integer rear = 0, front = 0;    

always @ (posedge w_clock)
    begin
        if ((front == 1 && rear == 8) || front == rear + 1)
            full = 1;

        else if(rear == 8)
            begin
                rear = 1;
                empty = 0;
            end

        else
            begin
                rear = rear+1;
                empty = 0;
            end
    end

    always @ (posedge r_clock)
    begin
        if (front == 0 && rear == 0)
            empty = 1;

        else if(front == 8)
            begin
                front = 1;
                full = 0;
            end

        else
            begin
                front = front+1;
                full = 0;
            end
    end
endmodule

Answer 1

You are using full and empty in left hand side of behavioral block (always). So they have to be registers. But at the same time they are output of counter and have to be wires. You can't use variables in that way.They can either be output of an instant and only used in right hand side of other parts of code or be regsietrs for using in left hand side of behavioral blocks that can also be input of another instant. You better change your coding style.

Here is an examole of async FIFO:

http://www.asic-world.com/code/hdl_models/aFifo.v

And also you need to study about blocking & nonblocking assignment and race conditions. Take a look at this:

http://ee.hawaii.edu/~sasaki/EE361/Fall01/vstyle.txt