Why assignment to wire datatype variable not allowed inside always block in verilog?

Question

我想知道为什么在verilog中的always块中不允许赋值给wire数据类型变量？

Answer 1

Wires ( nets ) were intended as a connection media and they do not keep value. So, you can use them for connecting modules, creating buses, ... There is a special 'assign' statement to assign them. Regs on the other hand were intended to represent registers and keep value. So, you cannot use them for connection, neither you can use wires as registers.

Saying that, all procedural blocks (always) are just small general-purpose programs with some extended semantics. But they use generic type of variables to keep intermediate values. Therefore out of the 2 types above only the 'reg' fits in this category. So, it only allow assignment to regs.

Well this concept creates a lot of headache for verilog programming. Therefore System Verilog came up with the logic datatype, which can replace both of them in most of the cases. You can use it either to connect things or to assign to it in the always blocks.

Answer 2

A wire in Verilog is very distinct concept from a variable . Although both are used to represent values that change over time, the way that obtain their values is very different. As in most other programming languages, you make a procedural assignment of a value to variable , and the variable holds that value until the next procedural assignment.

A wire represents a connection in hardware, or group of connections forming a network. That network is physically implemented as a metal wire on a chip or board. You can think of a wire as the transmission of a value from a driver to a receiver. In Verilog, drivers are represented by constructs that perform continuous assignments as opposed to procedural assignments.

I explain this in further detail in this post .

Answer 3

它只是因为在总是阻塞目标的情况下必须存储该值，除非并且直到新输入到达或灵敏度列表发生变化，另一方面导线无法做到。