Simulation results of verilog in modelsim

Question

For my assignment, I need to take the results of my verilog simuation in modelsim in the log files. I have taken the screenshot of the waveform window. Apart from this I have also taken the print out of the transcript window.

Is there any way to store the transcript into log file?

Please explain the commands to store my results of verilog simulation.

Answer 1

A .vcd file is an IEEE 1364-1995 standard file that contains all the simulation waveform information that is useful for debugging simulation. It contains all the signals in the design, so you do not need to rerun a simulation if you need to add a signal in the Waveform window.

To create a .vcd file:

1) Compile and load design successfully in transcript window

2) Specify VCD filename

• Syntax: vcd file .vcd

3) Enable VCD to dump signals under a desired instance

• Syntax: vcd add /*

Note: This command does not dump signals of children instances

                  Enable VCD for encrypted instances will generate warnings

4) Run simulation generate VCD database

5) Quit simulation

• Syntax: quit sim

To be able to display the signals in the .vcd file in Modelsim Waveform window:

  1)    Convert VCD to WLF format in ModelSim

• Syntax: vcd2wlf

Note: if the conversion fails, most of the time it is caused by non-existing instance path. Make sure the desired instance paths specified in step 3 are correct

2) Exit the current ModelSim session (needed for ModelSim for generate a proper VCD file)

3) ModelSim session and open the WLF file created in the step 1

• File menu -> Open -> file2.wlf

4) Select signals for debugging in Object window and add them to the Waveform window

answer is copy from https://www.altera.com/support/support-resources/knowledge-base/solutions/rd07062010_692.html