Using a generate with a parameter in verilog

Question

I'm trying to implement flip flops using a vector parameter:
if N[i] = 1 the code will implement a physical flop,
if N[i] = 0 the code will not implement a physical flop.

parameter N= 4'b0101;
reg [3:0] out ;
genvar i; 
generate 
for (i=0; i<4; i=i+1) begin : FF_GEN
   if (N[i]) 
       begin
          always @(posedge clk) 
             out[i] <= in[i];
       end 
   else 
      begin
         always @(*)
            begin
               out[i] = /*in[i] &*/ 1'b0; // without 'in' sim scheduler shouts
            end
      end
endgenerate

The questions:

1. Do you know a better way to implement a reg vector with these kind of "holes"?
2. I had to add the in[i] in the combo always since it needs something in the sensitivity list, otherwise the scheduler in the simulation won't execute the code line. "driver without sink" error. Do you have a better solution?

Answer 1

The use of a bit vector to generate registers (or not) is fine.

You can always assign a zero which makes that the register will be disappear during optimisation:

for (i=0; i<4; i=i+1) begin : FF_GEN
      always @(posedge clk) 
         out[i] <= N[i] ? in[i] : 1'b0;
end      

It may be that some tools do not like you to use ( * ) because they start looking for a right-hand-side variable and failing. In that case you could use 'in' for the sensitivity list.

 for (i=0; i<4; i=i+1) begin : FF_GEN
    if (N[i])      
       always @(posedge clk) 
              out[i] <= in[i];
    else    
      always @(in) // or ( * ) but that might not always work
         out[i] <= 1'b0;
  end 

The shortest form I can think of does not need generate at all:

always @(posedge clk) 
   out <= in & N;

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Post edit:
In the shortest form I rely on the synthesis tool to recognize that the result of some bits is always zero and thus will optimise the registers away. That can be prevented but you have to specifically add synthesis instructions to keep them.