I'm trying to modify a verilog netlist that looks like this:
module la_bla ( a b c d);
input a;
output;
inout c d;
uHBMN_1 X20 (.Z(en), .A(gg), .Q(qq), .EN(rr));
nch_mac M20 (.G(en), .D(gg), .B(qq), .S(rr));
pch_mac_svt M20 (.G(en), .D(gg), .B(qq), .S(rr));
endmodule
module la_bla2 ( aw b2 c1 dt);
input aw;
output b2;
inout c1 dt;
HBMN_2 X21 (.Z(en), .A(gg), .Q(qq), .EN(rr));
HBMN_3 X21 (.Z(env), .A(ggg7), .Q(qq), .EN(rr));
HBMN_4 X21 (.Z(en5), .A(gg), .Q(qq8), .EN(rr));
HBMN_5 X21 (.Z(en1), .A(gg), .Q(qq), .EN(rr));
endmodule
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Everytime that I find a line that start with a device called :"nch_mac" or pct_mac_svt, I want to add a comment to the ALL module content, but keep the module statement and terminals statements ( input , output inout) and endmodule statements untouched. I tried to work with perl flip-flop command:
First, I tried to catch the block that starts with module and finishes with endmodule. Then I tried to capture the device name with regex.
My problem is that required device name can be located anywhere inside the module statement - so how I comment the lines inside the module that comes before it?
I tried something like:
while<FILE>{
if(/module/i.../endmodule/i){
if($_ =~/nch_mac|pch_mac_svt){ $newline=~ s/$_/\/\/$_/}
But this didn't work.
I want to get:
module la_bla ( a b c d);
input a;
output;
inout c d;
//uHBMN_1 X20 (.Z(en), .A(gg), .Q(qq), .EN(rr));
//nch_mac M20 (.G(en), .D(gg), .B(qq), .S(rr));
//pch_mac_svt M20 (.G(en), .D(gg), .B(qq), .S(rr));
endmodule
module la_bla2 ( aw b2 c1 dt);
input aw;
output b2;
inout c1 dt;
HBMN_2 X21 (.Z(en), .A(gg), .Q(qq), .EN(rr));
HBMN_3 X21 (.Z(env), .A(ggg7), .Q(qq), .EN(rr));
HBMN_4 X21 (.Z(en5), .A(gg), .Q(qq8), .EN(rr));
HBMN_5 X21 (.Z(en1), .A(gg), .Q(qq), .EN(rr));
endmodule
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Any advise?
Store the lines in an array before you decide how you want to print them:
use warnings;
use strict;
my $flag = 1;
my @lines;
while (<DATA>) {
if (/(input|output|inout|\bmodule)/) {
print;
$flag = 1;
}
elsif (/endmodule/) {
for my $line (@lines) {
$line = "//$line" unless $flag;
print $line
}
print;
@lines = ();
}
else {
push @lines, $_;
if (/nch_mac|pch_mac_svt/) {
$flag = 0;
}
}
}
__DATA__
module la_bla ( a b c d);
input a;
output;
inout c d;
uHBMN_1 X20 (.Z(en), .A(gg), .Q(qq), .EN(rr));
nch_mac M20 (.G(en), .D(gg), .B(qq), .S(rr));
pch_mac_svt M20 (.G(en), .D(gg), .B(qq), .S(rr));
endmodule
module la_bla2 ( aw b2 c1 dt);
input aw;
output b2;
inout c1 dt;
HBMN_2 X21 (.Z(en), .A(gg), .Q(qq), .EN(rr));
HBMN_3 X21 (.Z(env), .A(ggg7), .Q(qq), .EN(rr));
HBMN_4 X21 (.Z(en5), .A(gg), .Q(qq8), .EN(rr));
HBMN_5 X21 (.Z(en1), .A(gg), .Q(qq), .EN(rr));
endmodule
Here is my exact output:
module la_bla ( a b c d);
input a;
output;
inout c d;
//
//uHBMN_1 X20 (.Z(en), .A(gg), .Q(qq), .EN(rr));
//nch_mac M20 (.G(en), .D(gg), .B(qq), .S(rr));
//pch_mac_svt M20 (.G(en), .D(gg), .B(qq), .S(rr));
endmodule
module la_bla2 ( aw b2 c1 dt);
input aw;
output b2;
inout c1 dt;
HBMN_2 X21 (.Z(en), .A(gg), .Q(qq), .EN(rr));
HBMN_3 X21 (.Z(env), .A(ggg7), .Q(qq), .EN(rr));
HBMN_4 X21 (.Z(en5), .A(gg), .Q(qq8), .EN(rr));
HBMN_5 X21 (.Z(en1), .A(gg), .Q(qq), .EN(rr));
endmodule
If your input Verilog code is more complicated than that, use a proper parser, such as Verilog-Perl
here is the full code that I wrote . it works but it can be improved. for example the line that start with "module" can be expand over few lines ( can be 2 lines, can be 100 lines) but it will always end up with char ";"
#!/usr/intel/bin/perl -w
use strict;
use Data::Dumper;
use Getopt::Long;
my $verilog1= "/p/ccd/wa/mlea/roodbridgetc/analog/roodbridgetc_9m1z1u/User_libs/libFlow/meny_lo cal/noam_tc_phy_ana_top/verilog/netlist";
my $verilog2= "/p/ccd/wa/mlea/roodbridgetc/analog/roodbridgetc_9m1z1u/User_libs/libFlow/meny_local/noam_tc_phy_ana_top/verilog/netlist2" ;
open(VERILOGA,"$verilog1") or die "Can't open original verilog file $verilog1 - $!\n";
open(VERILOGAA,">$verilog2") or die "Can't open destination verilog file $verilog2 - $!\n";
my $flag = 1;
my @lines =();
while (<VERILOGA>) {
if ($_ =~ /^input|^output|^inout|^module/) {
print VERILOGAA $_;
$flag = 1;
}
elsif($_ =~ /^\/\/|timescale|^`include|^\s*$/){print VERILOGAA $_ } ## this is for general information lines in verilog netlist
elsif($_ =~ /\s+{?\w+?(\[\d+\])?}?,?\s?\)?;?$/){print VERILOGAA $_ } ## this is for supporting the case that the "module line contain \n char or {} for bus or [*]
elsif($_ =~ /^\s+\)+?;$/){print VERILOGAA $_ }
elsif(/^endmodule/) {
for my $line (@lines) {
$line = "//$line" unless $flag;
print VERILOGAA $line;
}
print VERILOGAA $_;
@lines = ();
}
else{
push @lines, $_;
if(/^nch_mac
|^nch_18_mac
|^nch_svt_mac
|^nch_ulvt_dnw_mac
|^nch_lvt_mac
|^pch_lvt_mac
|^pch_18_mac
|^pch_svt_mac
|^nch_18_mac
|^pch_ulvt_mac
|^nch_ulvt_mac
|^crtmom_wo_rf
|^cfmom_2t_p80
|^nch_gate_sw
|^rhim_m
|^rhim_rf
|^nch_svt_dnw_mac
|^pwdnw
|^nch_lvt_dnw_mac
|^pch_18ud12_mac
|^pch_18ud15_mac
|^nch_ulvt_dnw_mac
/gx){
$flag = 0;
}#if
}#else
}#while
close VERILOGA;
close ;
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