How to replace combinational memory with ASIC cell in Chisel

Question

I am trying to do ASIC synthesis for Rocket processor which is written by Chisel. It automatically generates *.conf and *.behave_srams.v files. So, I can easily replace SeqMem with ASIC SRAM. However, for "Mem" which is combinational memory is always changed to register. How can I replace the Mem with ASIC combinational memory or ASIC register file? Is there an option for this when generating verilog?

Answer 1

Unfortunately, the current flow only supports replacing SeqMems. It would be nice for it to be extended to support combinational memories. Currently, your best bet would just be to instantiate your ASIC combinational memories as blackboxes directly in the Chisel.