XOR in always sensitivity list. Verilog

Question

有人可以解释这行中的情况吗？“总是@（posege（sclk ^（CPHA ^ CPOL））或posege spi_word_send”。我是verilog的初学者，不了解如何在敏感度列表中使用XOR。谢谢。

Answer 1

In general, procedural blocks can contain delay or wait-on-event statements that block the procedure until the time or event is satisfied. These statements are used in both simulation and synthesis for writing testbenches and describing logic; the flexibility of these constructs (like the # delay or the @ event wait) is rather extensive. However, when using these to actually describe hardware, you can only using these in limited situations.

Your case: @(posedge (sclk ^ (CPHA ^ CPOL)) or posedge spi_word_send) is simply saying Wait until either the expression sclk ^ CPHA ^ CPOL goes from low to high ( posedge ) or spi_word_send to go from low to high, then do the expressions contained in the always block (one example of the xor expression changing from low to high would be sclk = 1, CPHA = 1, CPOL = 0 becoming sclk = 1, CPHA = 1, CPOL = 1 , (1 ^ 1 ^ 0 = 0, 1 ^ 1 ^ 1 = 1).

The language allows you to have such complex wait expressions and simulation tools will generally run it as expected, but if the expression is supposed to be synthesized, you need to be sure you are actually describing the hardware you want. As toolic mentioned, this is not good style and is describing a flipflop with a rather complex clock signal (or maybe set/reset, the synthesis tool will try its best but it will probably generate something strange for this if it passes at all); its certainly asynchronous logic. Most designs are synchronous and synthesis tools generally are designed to handle synchronous designs when they are described behaviorally like the one above. As such, there are significant restrictions put on the always @ blocks, ie to be something like always @(posedge some_clock or negedge some_asserted_low_reset) , to make sure the code infer clean flipflops will clear clocks and resets.