Skipping the next instruction in mips32

Question

Suppose I want to develop a psuedoinstruction in MIPS that skips the next instruction after I call this skip instruction say skip $s0 .

I thought maybe I could use $jr on $s0 , but I would need to change the address of $s0 .

How could I approach this problem?

Answer 1

I want to develop a psuedoinstruction in MIPS that skips the next instruction

The simpler is to use a "branch" that is always verified.

beqc $0,$0,2

will replace PC by PC+(2*4) if $0==$0 (ie always) and skip next instruction.

This is a trick frequently used to process if-then-else

if(a1)
   a2=3;
else
   a3=4;

      beqc  $a1, $0, else
      addi $a2, $0, 3
      beqc  $0,  $0, 2 ; go to end of if then else
else: addi $a3, $0, 4
      # end of if-then else

beqc is a delay less branch introduced in mips64-v6 (along many other branch/jump with zero delay slots).

With older versions of the mips ISA, it is not possible to skip next instruction, as all branches execute the following instruction. To skip the second next instruction, the idea is the same.

beq $0,$0,2       ; delayed branch. execute next instruction and if test 
                  ;   is true (ie always) go to pc+4+2*4
add $0, $0, $0    ; aka nop (because of the delay slot)
xxx $a1, $a2, $a3 ; this instruction will be skipped
yyy $t1, $t2, $t3 ; and this instruction will be executed