How to dynamically generate module instance names in System Verilog?

Question

I have some parameterized Verilog and I need to dynamically generate instance module names, but I don't know how, within the confines of Verilog itself(ie without creating a script or similar to generate flat Verilog).

A bit of background, I have a large number of memory modules in a memory library. These are all named, approximately, MemModuleDepth_Width in a wide range of depths and widths. I have parameterized module that would like to use the memories from this library. However, to do this, I need to dynamically generate the module names, as shown below.

module fifo(in, out)
parameter width;
parameter depth;
...fifo stuff...
MemModule"depth"_"width" (read_address, read_data, etc.) <== where depth and width sweep in values
endmodule

This is not the typical use of something like a generate statement, and, as I have tried, also outside the scope of define macros, since the macros are expanded before the code body is parsed. This doesn't work:

`define DATAMEM(depth, width) MemModule``depth``_``width``
...
generate
    genvar i;
    for(i = 1; i <= depth; i = i++) begin : depth
        genvar j;
        for(j = 1; j <= width 0; j = j++) begin : width
            `DATAMEM(i, j) dpRam
        end
    end
endgenerate

This code simply tries to instantiate "MemModulei_j" rather than substituting the actual numerical values for i and j.

Any hints as to how one might do this?

Answer 1

You cannot build an identifier name except through the use of macros. As you pointed out, that will not work for parameter values.

If you had a manageable number of actual depth/width combinations you expect to use, you could create a generate-case/if construct tree

module MemModuleGeneric #(int depth, width) (...);
case (width)
  16: case (depth)
        16: MemModule16_16 M(read_address, read_data, etc.);
        24: MemModule16_24 M(read_address, read_data, etc.);
      endcase
  32: case (depth)
        16: MemModule32_16 M(read_address, read_data, etc.);
        24: MemModule32_24 M(read_address, read_data, etc.);
      endcase
endcase
endmodule