How to use trigger signals to set signals high after N cycles in verilog?

Question

I have a module(input:clk,reset,trL,trS;output:tL,tS;) .

I need to implement that

1. trL = 1, trS = 0: Make tL = 1 after 5 cycles.

2. trL = 0, trS = 1: Make tS = 1 after 2 cycles.

3. trL = 0 , trS = 0: No change.

reg [8:0] count;
always@(posedge clk)
if(reset)
count<=0;
else 
count=count+9'd1;

always@(posedge clk)
if(trL==1&&trS==0(only in one cycle not always be like this))

after 5 cycles, tL<=1(only in one cycle);

else if(trL==0&&trS==1(only in one cycle))

after 2 cycles, tS<=1( only in one cycle);

else if(trl==0&&trS==1)

tL<=tL,tS<=tS;

Answer 1

Okay here goes...

module trigger(
       clk,
       reset,
       trL,
       trS,
       tL,
       tS
     );

input clk;
input reset;
input trL;
input trS;
output tL;
output tS;

reg tL_d1;
reg tL_d2;
reg tL_d3;
reg tL_d4;
reg tL_d5;

reg tS_d1;
reg tS_d2;

wire tL_wire;
wire tS_wire;

 assign tL_wire = trL & ~trS;
 assign tS_wire = ~trL & trS;

always@(posedge clk or posedge reset)
begin
  if(reset)
  begin
    tL_d1 <= 1'd0;
    tL_d2 <= 1'd0;
    tL_d3 <= 1'd0;
    tL_d4 <= 1'd0;
    tL_d5 <= 1'd0;
  end
 else
 begin
   tL_d1 <= tL_wire;
   tL_d2 <= tL_d1;
   tL_d3 <= tL_d2;
   tL_d4 <= tL_d3;
   tL_d5 <= tL_d4;
 end
end

always@(posegde clk or posedge reset)
begin
  if(reset)
  begin
    tS_d1 <= 1'd0;
    tS_d2 <= 1'd0;
  end
  else 
  begin
    tS_d1 <= tS_wire;
    tS_d2 <= tS_d1;
  end
 end

assign tL = tL_d5;
assign tS = tS_d2;

endmodule

Edit !!!!! Hope this is what you are expecting

module trigger(
   clk,
   reset,
   trL,
   trS,
   dlya,
   dlyb,
   tL,
   tS
 );
input clk;
input reset;
input trL;
input trS;
input [2:0]dlya;
input [2:0]dlyb;
output tL;
output tS;

reg [2:0]count_a;
reg [2:0]count_b;

wire max_val_a;
wire max_val_b;

assign max_val_a = (count_a == dlya);
assign max_val_b = (count_b == dlyb);

reg cond1;
reg cond2;

always@(posedge clk or posedge reset)
begin
 if(reset)
   cond1 <= 1'd0;
 else if(max_val_a)
   cond1 <= 1'd0;
 else if(trL && !trS)
   cond1 <= 1'd1;
 end

always@(posedge clk or posedge reset)
begin
 if(reset)
   cond2 <= 1'd0;
 else if(max_val_b)
   cond2 <= 1'd0;
 else if(!trL && trS)
   cond2 <= 1'd1;
 end

always@(posedge clk or posedge reset)
begin
  if(reset)
     count_a <= 3'd0;
  else if(max_val_a)
     count_a <= 3'd0;
  else if(cond1)
     count_a <= count_a + 3'd1;
end

always@(posedge clk or posedge reset)
begin
  if(reset)
     count_b <= 3'd0;
  else if(max_val_b)
     count_b <= 3'd0;
  else if(cond2)
     count_b <= count_b + 3'd1;
end

assign tL = max_val_a & cond1;
assign tS = max_val_b & cond2;

 endmodule