One clock cycle delay in communication between one SC_CTHREAD and another SC_CTHREAD

Question

I am trying to model a simple direct mapped cache with main memory module which is an sc_cthread and a main memory state machine which also an SC_CTHREAD . I am observing one clock cycle delay from writing to a signal from my main memory module and receiving it on state machine.

How can I do it in only one clock cycle?

Answer 1

You cannot avoid the latency between threads when using an SC_CTHREAD. When writing to an sc_signal from one CTHREAD, the value change will only be visible to another CTHREAD at the next clock edge.

If you must use a CTHREAD (ie using high-level synthesis), then the only way to avoid the cross-thread latency is to place both functionalities within a single CTHREAD.

If you only need a behavioral model for simulation, then you could use SC_THREADs and sc_events. One thread can generate an sc_event that is being waited on by the second thread. When the second thread wakes on that event, it can observe sc_signal changes done by the first thread, and then produce an output (aligned with the clock edge if desired). Using sc_events gives the opportunity to sample and update signals "between" clock edges.