What is the meaning of “The illusion of shared memory on modern computer architectures” from the Akka actor documentation?

Question

I am beginning with actor model and have some problem in getting the concept behind, could you please explain in simple words with an example.

Answer 1

First, let's be clear what you are referencing. You are quoting from the opening documentation where it discusses why a new programming model is needed. I mention this because this is all very computer science theory, and not directly relevant to learning the API. Overall, I'd consider it a relatively minor point.

But, that paragraph of the docs gives a couple of examples already. The paragraph's point fundamentally being, that concurrency is inherently hard on a modern system, and that traditional concurrency APIs often create abstractions that have unintended performance consequences.

Specifically, the paragraph talks about how even if memory is "shared" via a concurrency API, that the realities of modern CPU architectures means that not all access is equal. That if a piece of data is created by thread 0 and it is used by thread 1, that the CPU architecture ends up invalidating that data on thread 0 and shipping the cache line over to thread 1. ie that even if the memory is marked as "shared" there is actually a significant performance penalty every time a different thread accesses that memory. The "shared" memory model is an illusion because the CPUs need to maintain a variety of caches that result in the memory not really being shared, but rather passed back and forth (at significant cost).

This is just one minor point of the opening justification, but it leads to some of the benefits of the concurrency provided by the Actor model. Since an actor has exclusive access to its state not only is the API simpler (because you don't have to worry about concurrency), but the physical CPU doesn't have to worry about that concurrency either. That not only do YOU not have worry about locks, but the CPU doesn't have to worry about locking either: it will be able to access memory without having to pass cache lines back and forth between phyiscal cores/CPUs.