"Target of concurrent assignment or output port connection should be a net type"

Question

I'm running into the following errors when trying to synthesize my code to run on my Anvyl board:

 ERROR:HDLCompiler:329 - "C:/Users/Chase/Desktop/Code 
 Templates/final_bcd_counter.v" Line 25: Target <digit_1> of concurrent assignment or output port connection should be a net type.

 ERROR:HDLCompiler:329 - "C:/Users/Chase/Desktop/Code 
 Templates/final_bcd_counter.v" Line 26: Target <digit_2> of concurrent assignment or output port connection should be a net type.

I was provided with a Lab_board.v file to drive the board which is as follows:

`timescale 1ns / 1ps

module lab_board(LED, SW, CLK);

output  [7:0] LED;
input  [7:0] SW;
input CLK;

bcd_count_7 counter( 
.max_count(SW[6:0]), 
.CLK(CLK), 
.run(SW[7]), 
.digit_l(LED[3:0]),
.digit_2(LED[7:4])
); 


endmodule

The code that the errors are throw in is my final_bcd_counter.v file which is the main driver of the program that passes all the needed values to the board. It is as follows:

// This is the top module for the programmable BCD counter.
// It implements a programmable 7-bit counter and a binary-
// to-bcd converter that can output two digits.


module bcd_count_7(max_count, CLK, run, digit_1, digit_2);

  input [6:0] max_count;
  input CLK, run;
  output reg [3:0] digit_1;
  output reg [3:0] digit_2;

  //Wires and registers for interconnect if needed
  wire [6:0] countin_out;

  // Programmable 7-bit counter module
  prog_count_7 counter(.max_count(max_count), 
            .run(run), 
            .CLK(CLK), 
            .count_out(countin_out));

  // Binary-to-BCD Converter for converting count_out to BCD
  binary_bcd_2 bcd_converter(.bin_in(countin_out),
                  .digit_1(digit_1), 
                  .digit_2(digit_2));

endmodule

I've tried changing the type of digit_1 and digit_2 with no avail. Could the solution be creating wires that connect to the lab board instead of passing output registers, if so, what would that look like?

Any help is appreciated. I can provide the code of the other modules in the program if needed.

Thanks!

Answer 1

You've declared digit_1/2 as a variable and it needs to be a net in Verilog I'm assuming those are output ports from your binary_bcd_2 module. SystemVerilog does not have this restriction.

Simply remove the reg keyword from the port declaration. I've added wire for clarity, but that is what is implicit

module bcd_count_7(
  input wire [6:0] max_count,
  input wire CLK, run,
  output wire [3:0] digit_1,
  output wire [3:0] digit_2
);