Concurrent assignment error in verilog

Question

My code is as follows:

   module trapverilog(
        input CLK,
        input SIGNALP,
         input SIGNAL1,
         input SIGNAL2,
         input SIGNAL3,
         input SIGNAL4,
         input SIGNAL5,
         input SIGNAL6,
         input SIGNAL7,
         input X1,
         input X2,
         input X3,
         input X4,
         input X5,
         input X6,
         input X7,
         input SUMP,
         input SUM1,
         input SUM2,
         input SUM3,
         input SUM4,
         input SUM5,
         input SUM6,
         input SUM7, // OUT pins are mapped to SUM pins on board
        output reg OUTP,
         output reg OUT1,
         output reg OUT2,
         output reg OUT3,
         output reg OUT4,
         output reg OUT5,
         output reg OUT6,
         output reg OUT7
        );

reg[6:0] yregone;
reg[6:0] yregtwo;
reg[6:0] sum;
reg[6:0] SUM;
assign SUM = {SUM1, SUM2, SUM3, SUM4, SUM5, SUM6, SUM7};
reg[7:0] SIGNAL;
assign SIGNAL = {SIGNAL1, SIGNAL2, SIGNAL3, SIGNAL4, SIGNAL5, SIGNAL6, SIGNAL7};
reg[6:0] x;
assign x = {X1. X2. X3. X4. X5, X6, X7};

always @(posedge CLK)
begin
    if (SIGNALP == 1)
    begin
        SIGNAL = SIGNAL * -1;
    end

    if (SUMP == 1)
    begin
        SUM = SUM * -1;
    end

    yregtwo = yregone;
    yregone = SIGNAL;

    if (yregtwo != 0)
    begin
        sum = ((yregone + yregtwo)*x/2) + SUM; //treats x as plain h, change if treated as h/2

        if (sum < 0)
        begin
            OUTP = 1;
        end

        OUT1 = sum[1];
        OUT2 = sum[2];
        OUT3 = sum[3];
        OUT4 = sum[4];
        OUT5 = sum[5];
        OUT6 = sum[6];
        OUT7 = sum[7];
    end
end

endmodule

It produces the errors

Target <SUM> of concurrent assignment or output port connection should be a net type.
Target <SIGNAL> of concurrent assignment or output port connection should be a net type.
Target <x> of concurrent assignment or output port connection should be a net type.

These errors come up on the lines defining SIGNAL , SUM , and x . I believed part of the problem was from these variables not being defined in the always loop, but doing that produced even more errors. What can I do to fix this?

The code is to implement the trapezoidal integration method in verilog. The large number of inputs is because I want to input the data in parallel instead of serially as it's faster. All inputs with the SIGNAL prefix are used in the SIGNAL variable, all inputs with the X prefix are used in the x variable, and so forth. A P at the end of the input name indicates that it's the parity bit. Numbers indicate which spot in the resulting register the bit should go.

Answer 1

You are assigning those signals in multiple places. You can't do that.

assign SUM = {SUM1, SUM2, SUM3, SUM4, SUM5, SUM6, SUM7};
assign SIGNAL = {SIGNAL1, SIGNAL2, SIGNAL3, SIGNAL4, SIGNAL5, SIGNAL6, SIGNAL7};
....
if (SIGNALP == 1)
begin
    SIGNAL = SIGNAL * -1;
end

if (SUMP == 1)
begin
    SUM = SUM * -1;
etc.

as to X:

assign x = {X1. X2. X3. X4. X5, X6, X7};
              ^   ^   ^   ^  Full stop????

Also you should use non-blocking assignments in your always @(posedge CLK) section.