Not getting the relevant output in my 32-bit ALU using gate-level verilog code

Question

Below is the code for 32 bit ALU with 3 different modules with their individual codes as well. I am not getting any warning now but I am also not getting the expected 32-bit output as shown in the figure below. No changes can be made in the stimulus as that is pre-defined. Below I am attaching the image of the ALU as well as the image of the output screen I am getting on running in the Xilinx.

       module shifter(
   output [31:0]   shifted_y
  ,input  [4:0]    x, Const_amount, const_var
  ,input  [31:0]   y
  ,input           shift_direction
);
wire [4:0] amount, m, n;

assign m = Const_amount & const_var; 
assign n = x && const_var;
assign amount = m || n;

assign shifted_y = (shift_direction == 1'b1) ? y << amount : y >> amount ;

endmodule

module fulladd(ss, cc, a, b, c);
output ss, cc;
input a, b, c;
wire s1, c1, c2;

//logic gates
xor (s1, a, b);
and (c1, a, b);
xor (ss, s1, c);
and (c2, s1, c);
or (cc, c2, c1);

endmodule

//////////////////32-bit adder/subtractor/////////////
module adder_sub (ss, cc, a, b, c);
output cc;
output [31:0] ss;
input[31:0] a, b;
input c;
wire [30:0] d; 
wire [31:0] t;

//instantiate and logic gates
xor x0(t[0], b[0], cc);
fulladd as0(ss[0], d[0], a[0], t[0], c);

xor x1(t[1], b[1], cc);
fulladd as1(ss[1], d[1], a[1], t[1], d[0]);

xor x2(t[2], b[2], cc);
fulladd as2(ss[2], d[2], a[2], t[2], d[1]);

xor x3(t[3], b[3], cc);
fulladd as3(ss[3], d[3], a[3], t[3], d[2]);

xor x4(t[4], b[4], cc);
fulladd as4(ss[4], d[4], a[4], t[4], d[3]);

xor x5(t[5], b[5], cc);
fulladd as5(ss[5], d[5], a[5], t[5], d[4]);

xor x6(t[6], b[6], cc);
fulladd as6(ss[6], d[6], a[6], t[6], d[5]);

xor x7(t[7], b[7], cc);
fulladd as7(ss[7], d[7], a[7], t[7], d[6]);

xor x8(t[8], b[8], cc);
fulladd as8(ss[8], d[8], a[8], t[8], d[7]);

xor x9(t[9], b[9], cc);
fulladd as9(ss[9], d[9], a[9], t[9], d[8]);

xor x10(t[10], b[10], cc);
fulladd as10(ss[10], d[10], a[10], t[10], d[9]);

xor x11(t[11], b[11], cc);
fulladd as11(ss[11], d[11], a[11], t[11], d[10]);

xor x12(t[12], b[12], cc);
fulladd as12(ss[12], d[12], a[12], t[12], d[11]);

xor x13(t[13], b[13], cc);
fulladd as13(ss[13], d[13], a[13], t[13], d[12]);

xor x14(t[14], b[14], cc);
fulladd as14(ss[14], d[14], a[14], t[14], d[13]);

xor x15(t[15], b[15], cc);
fulladd as15(ss[15], d[15], a[15], t[15], d[14]);

xor x16(t[16], b[16], cc);
fulladd as16(ss[16], d[16], a[16], t[16], d[15]);

xor x17(t[17], b[17], cc);
fulladd as17(ss[17], d[17], a[17], t[17], d[16]);

xor x18(t[18], b[18], cc);
fulladd as18(ss[18], d[18], a[18], t[18], d[17]);

xor x19(t[19], b[19], cc);
fulladd as19(ss[19], d[19], a[19], t[19], d[18]);

xor x20(t[20], b[20], cc);
fulladd as20(ss[20], d[20], a[20], t[20], d[19]);

xor x21(t[21], b[21], cc);
fulladd as21(ss[21], d[21], a[21], t[21], d[20]);

xor x22(t[22], b[22], cc);
fulladd as22(ss[22], d[22], a[22], t[22], d[21]);

xor x23(t[23], b[23], cc);
fulladd as23(ss[23], d[23], a[23], t[23], d[22]);

xor x24(t[24], b[24], cc);
fulladd as24(ss[24], d[24], a[24], t[24], d[23]);

xor x25(t[25], b[25], cc);
fulladd as25(ss[25], d[25], a[25], t[25], d[24]);

xor x26(t[26], b[26], cc);
fulladd as26(ss[26], d[26], a[26], t[26], d[25]);

xor x27(t[27], b[27], cc);
fulladd as27(ss[27], d[27], a[27], t[27], d[26]);

xor x28(t[28], b[28], cc);
fulladd as28(ss[28], d[28], a[28], t[28], d[27]);

xor x29(t[29], b[29], cc);
fulladd as29(ss[29], d[29], a[29], t[29], d[28]);

xor x30(t[30], b[30], cc);
fulladd as30(ss[30], d[30], a[30], t[30], d[29]);

xor x31(t[31], b[31], cc);
fulladd as31(ss[31], cc, a[31], t[31], d[30]);

endmodule

module logic(
   output      out
  ,input       p, q
  ,input [1:0] s
);

  wire ns0, ns1;
  wire w0,w1,w2,w3;
  wire t1,t2,t3,t4;

  and  u_gate_inst_0(t1,p,q);
  or   u_gate_inst_1(t2,p,q);
  xor  u_gate_inst_2(t3,p,q);
  nor  u_gate_inst_3(t4,p,q);

  not u_mux_inst_0 (ns0, s[0]);
  not u_mux_inst_1 (ns1, s[1]);
  and u_mux_inst_2 (w0 , t1, ns0 , ns1   );
  and u_mux_inst_3 (w1 , t2, ns1 , s[0]  );
  and u_mux_inst_4 (w2 , t3, ns0 , s[1]  );
  and u_mux_inst_5 (w3 , t4, s[0], s[1]  );
  or  u_mux_inst_6 (out, w0, w1, w2, w3);

endmodule

module logic_unit(
    output [31:0] out
   ,input  [31:0] p,q
   ,input  [1:0]  s
);

 logic logic_m1 [31:0] (out,p,q,s);

endmodule

module mux32bit(i0, i1, i2, sel, muxout);
input [31:0] i0, i1, i2;
input [1:0] sel;
output [31:0] muxout;
reg [31:0] muxout; 

always @ (i0 or i1 or i2 or sel)

    begin
     case (sel)
     2'b00: muxout = i0;
     2'b01: muxout = i1;
     2'b10: muxout = i1;
     2'b11: muxout = i2;
     default: muxout = 2'bx;
     endcase
   end
endmodule

//--------stimulu/s module
// The ALU module name and orders of inputs, outputs should be same as the ALU module in the following
module ALU_32bits(output [31:0] s, input [31:0] a, b, input c_0, 
input Const_Var, shift_direction, input [1:0] Function_class, input [1:0] Logic_function, input [4:0] Const_amount);

wire [31:0] adder_out, shifter_out, logic_out;
wire [4:0] const_var;
wire [1:0] sel;

mux32bit mux_output(shifter_out, adder_out, logic_out, sel, s);
shifter shifter_output(shifter_out, a[4:0], Const_amount[4:0], const_var[4:0], b, shift_direction);
adder_sub adder_sub_output(adder_out, cc, a, b, c);
logic_unit logic_output(logic_out, a, b, s[1:0]);

endmodule

module stimulus;

//inputs
reg[31:0] A,B;
reg C_0,Const_Var,shift_direction;
reg [1:0] Function_class;
reg [1:0] Logic_function;
reg [4:0] Const_amount; 

//outputs
wire[31:0] s;

ALU_32bits my_ALU (s,  A, B,  C_0, Const_Var, shift_direction, Function_class, Logic_function, Const_amount);

initial  
begin 

$monitor($time,"A=%d, B=%d, C_IN=%b,-- Function_class=%d, shift_direction=%b, Const_Var=%b, Const_amount=%d, shift_direction=%b, Logic_function=%d,--OUTPUT=%d \n",A,B,C_0,Function_class,shift_direction,Const_Var,Const_amount,shift_direction,Logic_function,s);
end

initial
begin
A=4'd0; B=4'd0; C_0=1'b0;
#5 A=8'd19; B=8'd55; Function_class[1]=1; Function_class[0]=0;  
#5 A=8'd59; B=8'd168;C_0=1'b1; Function_class[1]=0; Function_class[0]=1;  
#5 A=8'd39; B=8'd136; C_0=1'b1;  Function_class[1]=1; Function_class[0]=0; 
#5 A=16'd9; B=8'd112; Function_class[1]=0; Function_class[0]=0; shift_direction=1; Const_Var=1; 

#5 A=16'd129; B=16'd456;Function_class[1]=0; Function_class[0]=0;shift_direction=0;Const_Var=0;Const_amount=5'd7;  
#5 A=16'd656; B=8'd218; C_0=1'b0;Function_class[1]=1; Function_class[0]=1;Logic_function=2'd0;  
#5 A=8'd195; B=8'd228; C_0=1'b1;Function_class[1]=1; Function_class[0]=1;Logic_function=2'd1; 
#5 A=8'd99; B=16'd286; C_0=1'b1;Function_class[1]=1; Function_class[0]=1;Logic_function=2'd2; 
#5 A=8'd77; B=16'd486; C_0=1'b0;Function_class[1]=1; Function_class[0]=1;Logic_function=2'd3; 
end

endmodule

Image of ALU

Image of the output

Answer 1

If you can't modify the stimulus code, you can lookup your working version of Xilinx ISE or Vivado user manual, you didn't mention the platform you are using, on how to turn off warning flags for truncation. Note that the truncation will still happen, but you only won't be notified for it.

Answer 2

one thing can i say, in the elaborated design from the code you have provided observing many top ports are not connected to lower level modules.Please fix those connection issues and revert back the code so someone in the community can help you. please use Ansi-C style of verilog ports and named port connection while instantiating the modules,this type of coding style will be helpful for any modification, readability and to understand the code at a single glance.