How is an interrupt enabled and disabled in the IRQ on the processor side? [STM32]

Question

From what I understand, the interrupts are enabled by using the below approach: The steps 1) through 9) are followed in a general EXTI programming.

There are two sides for enabling and clearing the interrupt:

1. Peripheral Side: gets enabled by SYSCFG, EXTI blocks and also cleared in the pending register EXTI_PR once interrupt is encountered.
2. Processor Side: NVIC->ISER to enable. But in spite of NVIC->ICPR being there I don't see that it's being used to clear the processor side for pending register. Why?
3. Are there any peripheral side interrupt generators too which also don't have any pending register that required to be cleared?
4. Any document which explains these also would be greatly appreciated.

Answer 1

1. It is the same with all other peripheral registers. The clear path is not important from the programmer point of view. The important is information how to clear the bit.

2. Clear the bit you need to clear bit EXTI PR register.

3. Clearing sometimes happen indirectly (for example by reading the data register in some communication registers). Some peripherals have special registers only for clearing the pending bit. Example: DMA

Everything is in the Reference Manual.

Clearing the flag in the peripheral register deasserts the interrupt line coming to NVIC form peripheral.