Verilog bitwise XOR on 1-bit signal

Question

What would happen if a bitwise XOR operation is done on a 1-bit signal in Verilog.

For example:

input A;
wire B;
B = ^A;

If A is 1, would B be 1? or would it be X or something?

Answer 1

The code you show is known as a reduction XOR . Refer to IEEE Std 1800-2017, section 11.4.9 Reduction operators . These operators are intended to be used on signals of more than 1 bit, for example if A were 4 bits wide. In your case (1-bit), the behavior is not clearly defined. What kind of hardware are you trying to describe with that code? An XOR is used to compare 2 signals.

module tb;

reg A;
wire B = ^A;

initial begin
    $monitor($time, " A=%b  B=%b", A, B);
    #5 A = 0;
    #5 A = 1;
    #5 A = 0;
    #5 $finish;
end

endmodule

This is the output I get on 2 different simulators:

               0 A=x  B=x
               5 A=0  B=0
              10 A=1  B=1
              15 A=0  B=0

However, since this behavior is not clearly defined, you should not rely upon these results. You should avoid writing code that way.