SystemVerilog always @ sequence

Question

I want to create an always block that uses a sequence for the event control, but I'm not sure if that's allowed in SystemVerilog and I'm getting an internal compiler error when I try to do it. Here's a sample of my code:

sequence ReqValid_s;
  @(posedge clk)
  (ReqValid ##1 1) or (ReqSpec ##1 !ReqCancel);
endsequence

always @(ReqValid_s iff enable) begin
    //do stuff
end

When I try to compile this, I'm getting an internal compiler error without any helpful comment. I'm fairly confident it's due to the always @(ReqValid_s) because if I change it to always @(posedge clk) it works just fine. I haven't found any definitive answer in the SV LRM, but I thought this would work since I'm able to use a sequence for the sampling event of a covergroup.

Answer 1

This should have worked (you should never see an internal error). I would move the iff enable logic into the sequence. That way all signals will have the same sampling.

sequence ReqValid_s;
  @(posedge clk)
  (ReqValid ##1 enable) or (ReqSpec ##1 !ReqCancel && enable);
endsequence

always @(ReqValid_s) begin
    //do stuff
end