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Access specifier in SystemVerilog

原文 2016-04-19 10:03:51 2 1 verilog/ system-verilog

I am totally confused in access specifiers local , static , virtual , protected and automatic . give example or document for the same. Any Help appreciated a lot.

1 answers

These access specifiers apply to class member declarations (variables, functions and tasks declared within a class)

local : these members may only be reference from within the class is is declared in.
static : these members are allocated up declaration of a class and are shared between all constructed objects
virtual : apply to class methods(tasks and functions) and are better explained here and here .
automatic : never used in the declaration of a class or any of its members.

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Access specifier in SystemVerilog

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solution1 1 2016-04-19 13:50:27

solution1
1 2016-04-19 13:50:27