wire output shows nothing in verilog simulation code

Question

It is a simple asynchronous 2 bit counter, two JK flipflops are being used.

Here is my TwoBitCounter.v script.

`timescale 1ns / 1ps
    
    module TwoBitCounter(
        input wire clk,
        output wire q0,
        output wire q1
        );
    JK jk1(1, 1, clk, q0);
    JK jk2(1, 1, q0, q1);
    
    endmodule
    
    module JK(
        input wire J,
        input wire K,
        input wire clk,
        output reg out
        );
        
    always @(posedge clk) begin
        if(J==0&&K==0)
            begin end
        else if(J==0&&K==1) begin
            out <= 1'b0; 
        end else if(J==1&&K==0) begin
            out <= 1'b1;
        end else if(J==1&&K==1) begin
            out <= ~out;
        end
    end
    endmodule

and this is my simulation code:

    `timescale 1ns / 1ps
    
    module TwoBitCounter_sim();
    reg clk;
    wire q0;
    wire q1;
    
    TwoBitCounter twoBitCounter(.clk(clk), .q0(q0));
    
    initial clk = 1'b0;
    always clk = #100 ~clk;
    
    initial begin
        #1000;
        $finish;
    end
    
    endmodule

I have checked that JK module works properly alone. I tried disabling one JK flip flop to see if it has no errors while implemented in TwoBitCounter module, and it also did not work. Although I have checked several times to see if the algorithm itself is wrong, but got no clue what the fundamental problem is.

Answer 1

In your code there is only one J/K combination which you use: 1/1 . In this state you just invert the out (out <= ~out). However you had never initialized it. Your out initially has x value. Inversion of x is also x . So, it never changes.

You need to figure out a way to initialize the flops either by manipulating J/K values or by other means.

As an example, adding initial out = 0; in the JK module will change the picture, but it will not play well with synthesis. So, you need to figure out your own way.