DMA writing to allocated memory misses the first two adresses on the first write

Question

I'm playing around with a ZYNQ7 (Dual-Core ARM) with a FPGA. The FPGA design has a 32-bit counter accessing the DDR via a DMA controller in chunks of 256-packets.

In the C-Code for the processor 1, I run a LWIP application to connect via ethernet to my pc. There I allocate ram memory for the DMA transactions. The address of the pointer is passed via shared memory to the 2nd Core.

#define RCVADDR 0x1ef00002
u32_t * send=NULL;
u32_t* addr = (uint32_t*)RCVADDR;

//Allocating the memory once initially
if(send==NULL){
        send=malloc(256*sizeof(uint32_t));
    }

    *addr = (uint32_t)send;
    //starting the DMA on Core 2
    *getdma=1;

Using a handshake I initialize the DMA transactions in the second core and send the Data after finished transactions to the PC using a TCP connection on the 1st Core.

#define GetDMA  0x1ef00001
#define DONEDMA 0x1ef00003

uint8_t* getdma = (uint8_t*)GetDMA;
uint32_t* addr=(uint32_t*)RCVADDR;

    while(1){
        if(*getdma == 1){
            StartDMATransfer(*addr, 2048);  // The Number 2048 is the number Of Transfered Packets. It has to be at least the amount of Packets my Counter transfers in chunks. The design has a packet end indicator on its own. So 256 or bigger works the same as 256
            *getdma =0;

            Xil_DCacheFlush();

        }
    }

Before establishing a TCP-connection I flush the DCache

void send_data(){
    int ip_addr[4];
        u8_t i=0;

        char * token = strtok(ip,".");
        ip_addr[0] = atoi(token);

        while(token != NULL){

            ip_addr[++i]=atoi(strtok(NULL,"."));
        }
        Xil_DCacheFlushRange(send, 256*sizeof(uint32_t));

        //sleep(0.5);
        connect(ip_addr,atoi(port));
}

The Problem: The first Transmission Cycle after programming the Device shows:

[1280, 1281, 2, 3, 4, 5, 6,..... ....., 248, 249,1530, 1531, 1532, 1533, 1534, 1535]

The first 2 Values and the last 6 values are from a previous Cycle before reprogramming the device. However, this only occurs on the first DMA Transaction. Afterwards, while the device runs it never occurs once again.

Any Ideas?

Answer 1

I found a solution....

I had to flush the Cache after allocating the memory, before passing the address to the 2nd Core for processing.