XOR of variables in consecutive clock cycle

Question

I am just learning to code in verilog. I want to XOR three variable in consecutive clock cycles. For example Z1 from 1st clock cycle,Z2 from 2nd clock cycle and Z3 from 3rd clock cycle. How can I do that.

I have written something as below

always @ (posedge clk) begin
  lamda = Y1;
 #10 lamda = lamda^ Y2;
 #10 lamda = lamda ^ Y3;
end

where clock is taken as always #5 clk=~clk But it doesn't seem to work as expected. Can someone help me to fix it.

Answer 1

An important thing to keep in mind is # delays are only for simulation, and can't get synthesized. Therefore, you might want to switch to a counter to track which clock cycle you're on, and mux to select which input you're XORing. Something like this should work:

logic [1:0] counter; // counter resets to 0, counts up every clock cyle, and stops at 3
always_ff @(posedge clk, posedge reset) begin
    if (reset) counter <= 2'b00;
    else counter <= (counter == 2'b11 ? counter : counter + 1);
end

always_ff @(posedge clk) begin
    case (counter)
        2'b00: lambda <= lambda ^ Y1; // lambda gets (lambda xor Y1) on the rising edge of clk if counter is 0
        2'b01: lambda <= lambda ^ Y2; // lambda gets (lambda xor Y2) on the rising edge of clk if counter is 1
        2'b10: lambda <= lambda ^ Y3; // lambda gets (lambda xor Y3) on the rising edge of clk if counter is 2 
        default: lambda <= lambda ; // if anything else, lambda will just stay as lambda
    endcase
end

Answer 2

I'm not sure if this will work as you did not share whole code with us, but maybe below excerpt will do the job:

reg lamda_1,lamda_2,lamda_3;
always @ (posedge clk) begin
  lamda_1 = Y1;
  lamda_2 = lamda1 ^ Y2;
  lamda_3 = lamda2 ^ Y3;
end

But for sure you don't understand basics of HDL language, I'd recommend starting from getting through any kind of material explaining how always block works in verilog language (in internet you can find plenty of presentations explaining it).